The present invention relates in general to communication systems, and is particularly directed to a new and improved backplane architecture for digital telecommunication equipment that has the capability of providing for the asymmetric interchange of time slot data among multiple pieces of time division multiplexed communication equipment installed in respective card slots of the backplane.
Time division multiplexed (TDM) data communication equipment currently employed by telecommunication network service providers is typically configured to accommodate a prescribed number of data communication channels or time slots, respectively associated with various customer premises devices (e.g., data terminal equipments or DTEs). As a non-limiting illustration, a T1 network link contains twenty-four DS0 channels or time slots, within each of which eight bits of data are serially transmitted.
At a hub site, where routing calls among various users of the network is controlled, it is necessary to provide for the cross-connect or interchange of time slots/channels among respective ports of the TDM routing equipment. This may sometimes entail the transfer of a set or group of successively contiguous time slots of the TDM link porting one (source) circuit card to the TDM link porting another (destination) circuit card. Because conventional serial bus-based TDM routing equipment employs bus segmentation, which is not designed to route a multiple DS0 call across multiple serial bus segments, then if the TDM segment of the latter (destination) circuit card does not have the requisite number (or segment) of successively contiguous time slots, servicing the calls associated with the channels of interest is impaired, and utilization of the available bandwidth of the TDM link is reduced, until the required set of contiguous time slots become available. Because conventional serial bus-based TDM routing equipment is based upon symmetrical data transfer, full utilization of bandwidth is not realized with new asymmetrical data communication technologies.
In accordance with the present invention, the above described problems are effectively solved by a new and improved asymmetric TDM telecommunication time slot-routing backplane architecture that is parallel bus-based, rather than serial bus-based, which allows the data to be clocked at frequency reduced by a factor of the data size (by a factor of eight for a standard eight bits-per time slot serial format), thereby allowing the use of less costly components distributed among individual interfaces, and decreasing EMI (electromagnetic interference) effects attributed to higher bus clock speeds. The backplane architecture according to the present invention includes respective data, address and control bus portions along which interface circuit card slots served by the backplane are installed.
The data bus portion is a multi-bit parallel data bus, having a data width corresponding to the number of data bits conveyed over a TDM channel during a respective channel time slotxe2x80x94typically eight bitsxe2x80x94for a DS0 time slot, as noted above. Respective time slot data packets to be asserted onto the parallel data bus are converted from serial format to parallel format by serial-to-parallel conversion circuitry of a respective port""s interface circuit card. Conversely, data read from the parallel data bus for delivery to a destination device is converted back into serial format by parallel-to-serial conversion circuitry within a respective port""s interface circuit card.
The address bus portion of the backplane has a plurality of card or interface select lines and a multi-bit, parallel channel/time slot address bus. The number of select lines corresponds to the number of physical interface card slots of the backplane. An interface circuit card slot decoder of a backplane controller decodes the contents of respectively addressed memory locations of a time slot assignment memory of the backplane controller into card slot selection signals. The multi-bit parallel address bus is coupled to a portion of the time slot assignment memory""s data bus used to address a particular time slot/channel in an interface circuit card selected by the card slot decoder. As will be described, the direction of data flow with respect to the backplane depends upon the clock edge polarity of a backplane clock signal.
Data asserted onto the data bus during the talk or transmit portion of a respective time slot clock cycle is read from that memory location of the time slot memory of a source interface circuit card as selected by a respective card select line, and having an address associated with the particular time slot/channel identified by the contents of the card slot link. Data read from the data bus during a listen or receive portion of a respective time slot clock cycle is written into a storage location of a time slot memory of a destination interface circuit card as selected by a respective card select line, and having an address associated with the particular time slot/channel.
The data contents of respective memory location within the time slot assignment memory of the backplane controller include a card slot code and a channel select code, which define time slot or channel interchange (DS0 cross connect) assignments representative of which time slots of circuit cards being served by the backplane are to be interchanged, as specified in a time slot memory map. Once loaded into the time slot assignment memory, the time slot exchange memory map is sequenced by an address counter within the bank controller, so as to generate respective source and destination slots associated with the channel interchange among the various interface circuit cards.
Exercizing the dual page memories of the interface circuit cards on a per time slot basis provides two major benefits. First, cross-connect data flow can be either symmetric (the same number of time slots are exchanged between the network and a termination equipment site) or non-symmetric data (the number of time slots transferred from the network to a termination equipment site is different from the number of time slots transferred from a termination equipment site to the network). Secondly, all of the available bandwidth of the backplane is fully utilized.
A respective interface circuit card (network interface circuit card or subscriber-associated interface circuit card) includes a dual port, multi-page time slot/channel data random access memory having respective memory pages, read/write access to which is carried out in ping-pong fashion, so that when one page is in interface mode, the other page is in backplane mode. Each location of the channel data memory stores the (eight bit) data contents of a respective (64 Kbps) DS0 time slot.
For interfacing with the backplane, the dual page time slot data memory has a first data port coupled to the backplane""s multi-bit parallel data bus, and a first N-bit wide address port coupled to the multi-bit parallel channel/time slot address bus from the bank controller. For interfacing with a network or customer device interface, such as a data terminal equipment (DTE) interface ported to DTE equipment served by the backplane, the channel data memory has a data port coupled to a parallel data bus. The parallel data bus is coupled to serial-to-parallel and parallel-to-serial conversion circuitry within the DTE interface. In order to address the channel data memory, the interface includes an address counter to which a prescribed clock, such as a 2.048 MHz clock signal supplied by a DTE, is coupled.
In operation, listen and talk modes occupy alternate one-half portions of successive cycles of a bus clock. A frame synchronization reset signal overlaps the last time slot of a frame Fi and the first time slot of the next frame Fi+1. During the talk or transmit half cycle, whichever page of the channel data memory is not currently being accessed (loaded) by its associated address counter is accessed under the control of the DS0 assignment memory in the bank controller. As the bank controller""s DS0 assignment memory is sequentially addressed, respective card select lines, as decoded by the card slot decoder, are asserted valid on the falling edge of a TDM clock signal. The contents of that memory location identified by the multi-bit parallel channel/time slot address bus in the other page of the data memory of the interface card selected by the enabled card select line will be asserted onto the backplane bus on the falling edge of the clock signal.
In the listen mode, data that has been accessed/read out of one of the pages of memory of another (or the same) interface card and placed onto the backplane data bus during the previous talk mode half-cycle is written into one of the dual pages of memory of that other (or the same) interface card. At the same time, data that has been previously written into the other page of dual memory of that respective interface card is accessed/read out therefrom and converted into serial format for delivery to a destination device to which that respective interface card is coupled. Since the listen mode occurs in alternate half cycles with the talk mode, the time slots are enabled on the opposite (rising) clock edges of the bus clock signal.
Thus, as the DS0 channel assignment memory is sequentially addressed, respective card select lines as decoded by card slot decoder will be asserted valid by alternative falling edges of the bus clock signal. The contents of that memory location identified by the multi-bit parallel channel/time slot address bus of one of the two pages of the channel data memory of the interface card selected by the enabled card select line are written onto the backplane bus. The listen port of the card of interest will latch the TDM data on the next successive falling edge of the TDMCLK signal. Also, whichever page of the channel data memory not currently being accessed by the multi-bit parallel channel/time slot address bus is accessed under the control of the address counter, with the read out parallel byte of data then serialized out to an associated network or subscriber device.